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12-bit r/d converter with reference oscillator ad2s1200 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2003 analog devices, inc. all rights reserved. features complete monolith ic r/d converter parallel and serial 12-bit data ports system fault detection absolute position and velocity outputs differential inputs 11 arc minutes of accuracy 1,000 rps maximum tracking rate, 12-bit resolution incremental encoder emulation (1,024 pulses/rev) programmable sinusoidal oscillator on-board compatible with dsp and spi? interface standards 204.8 khz square wave output single-supply operation (5.00 v 5%) ? 40c to +125c temperature rating 44-lead lqfp package 4 kv esd protection general description the ad2s1200 is a complete 12-bit resolution tracking resolver- to-digital converter, integrating an on-board programmable sinusoidal oscillator that provides sine wave excitation for resolvers. an external 8.192 mhz crystal is required to provide a precision time reference. this clock is internally divided to generate a 4.096 mhz clock to drive all the peripherals. the converter accepts 3.6 v p-p 10% input signals, in the range of 10 khz to 20 khz on the sin and cos inputs. a type ii servo loop is employed to track the inputs and convert the input sin and cos information into a digital representation of the input angle and velocity. the bandwidth of the converter is set internally to 1.7 khz with an external 8.192 mhz crystal. the maximum tracking rate is 1,000 rps. functional block diagram 04406-0-001 reference oscillator (dac) adc sinlo sin angle angle adc coslo cos exc exc a b nm sample monitor error monitor (204.8khz) cpo refbyp refout fs1 fs2 xtalout clkin (8.192mhz) dos lot dir (4.096mhz) error error calculation/ signal monitor demodulator cs rd position integrator position register multiplexer db11 so soe rdvel reset db10 sclk db9?db0 ad2s1200 data bus output velocity register encoder emulation synthetic reference voltage reference internal clock generator clock divider fault indicators digital filter velocity integrator figure 1.
ad2s1200 rev. 0 | page 2 of 24 applications electric power steering electric vehicles integrated starter generator/alternator encoder emulation automotive motion sensing and control product highlights ? complete resolver-to-digital interface: the ad2s1200 provides the complete solution for digitizing resolver signals (12-bit resolution) with on-board programmable sinusoidal oscillator. ? ratiometric tracking conversion: this technique provides continuous output position data without conversion delay. it also provides noise immunity and tolerance of harmonic distortion on the reference and input signals. ? triple format position data: absolute 12-bit angular binary position data accessed either via a 12-bit parallel port or via a 3-wire serial interface. incremental encoder emulation in standard a quad b format, with direction output is available. ? digital velocity output: 12-bit signed digital velocity, twos complement format, accessed either via a 12-bit parallel port or via a 3-wire serial interface. ? programmable excitation frequency : excitation fre- quency easily programmable to 10 khz, 12 khz, 15 khz, or 20 khz by using the frequency select pins. ? system fault detection: a fault detection circuit will detect any loss of resolver signals, out of range input signals, input signal mismatch, or loss of position tracking.
ad2s1200 rev. 0 | page 3 of 24 table of contents ad2s1200Cspecifications ................................................................4 absolute maximum ratings ............................................................6 esd caution ..................................................................................6 pin configuration and function descriptions .............................7 resolver format signals ...................................................................8 principle of operation......................................................................9 fault detection circuit.................................................................9 connecting the converter .........................................................11 absolute position and velocity output ....................................12 parallel interface..........................................................................12 serial interface.............................................................................14 incremental encoder outputs...................................................16 on-board programmable sinusoidal oscillator.....................16 supply sequencing and reset....................................................17 charge pump output .................................................................17 circuit dynamics ............................................................................18 ad2s1200 loop response model ............................................18 sources of error ..........................................................................19 clock requirements ...................................................................20 connecting to the dsp...............................................................20 outline dimensions........................................................................21 ordering guide ...........................................................................21 revision history revision 0: initial version
ad2s1200 rev. 0 | page 4 of 24 ad2s1200Cspecifications table 1. (av dd = dv dd = 5.0 v 5% @ ?40c to +125c clkin 8.192 mhz, unless otherwise noted.) parameter min typ max unit conditions/comments sin, cos inputs 1 voltage 3.24 3.6 3.96 v p-p sinuso idal waveforms, differential inputs input bias current 2 a v in = 3.96 v p-p input impedance 1.0 m? v in = 3.96 v p-p common mode volts 100 mv peak cmv @ sinl o, coslo, with respect to refout @ 10 khz phase lock range ?45 +45 degrees sin/cos vs. exc output angular accuracy angular accuracy 11 arc min zero acceleration y grade 22 arc min zero acceleration w grade resolution 12 bits guaranteed no missing codes linearity inl 2 lsb zero acceleration, 0 to 1,000 rps linearity dnl 0.3 lsb guaranteed monotonic repeatability 1 lsb hysteresis 1 lsb velocity output velocity accuracy 2 lsb zero acceleration resolution 11 bits linearity 1 lsb guaranteed by design 2 lsb max offset 0 1 lsb zero acceleration dynamic ripple 1 lsb zero acceleration dynamic performance bandwidth 1,500 1,700 2,000 hz fixed tracking rate 1,000 rps guaranteed by design. tested to 800 rps. acceleration error 30 arc min at 10,000 rps 2 settling time 179 step input 4.72 5. 0 ms to within stated accuracy settling time 179 step input 3.7 3.8 ms to within one degree exc, exc outputs voltage 3.34 3.6 3.83 v p-p load 100 a center voltage 2.39 2.47 2.52 v frequency 10 khz fs1 = high, fs2 = high 12 khz fs1 = high, fs2 = low 15 khz fs1 = low, fs2 = high 20 khz fs1 = low, fs2 = low exc/exc dc mismatch 35 mv thd ?60 ?55 db first five harmonics fault detection block los sin/cos threshold 2.86 2.92 3.0 v p-p dos and lot go low when sin or cos fall below threshold. angular accuracy (worst case) 45 degrees los indicated before angula r output error exceeds limit (3.96 v p-p input signal and 2.9 v los threshold). angular latency (worst case) 90 degrees maximum electrical rotation before los is indicated (3.96 v p-p input signal and 2.9 v los threshold). time latency 125 s 1 the voltages sin, sinlo, cos, and coslo relative to agnd must always be between 0.2 v and av dd .
ad2s1200 rev. 0 | page 5 of 24 parameter min typ max unit conditions/comments fault detection block (cont.) dos sin/cos threshold 4.0 4.09 4.2 v p-p dos goes low when sin or cos exceeds threshold. sin/cos mismatch 385 420 mv dos latched low when sin/cos amplitude mismatch exceeds the threshold. angular accuracy (worst case) 30 degrees dos indicated before angu lar output error exceeds limit. angular latency (worst case) 60 degrees maximu m electrical rotation before dos is indicated. time latency 125 s lot tracking threshold 5 degrees lot goes low when internal error signal exceeds threshold. guaranteed by design. time latency 1.1 ms hysteresis 4 degrees guaranteed by design voltage reference refout 2.39 2.47 2.52 v iout = 100 a drift 70 ppm/c psrr ?60 db charge pump output (cpo) frequency 204.8 khz square wave output duty cycle 50 % power supply i dd dynamic 18 ma electrical characteristics v il voltage input low 0.8 v v ih voltage input high 2.0 v v ol voltage output low 0.4 v 2 ma load v oh voltage output high 4.0 v ?1 ma load i il low level input current 10 a i ih high level input current ?10 a i ozh high level three-state leakage ?10 a i ozl low level three-state leakage 10 a
ad2s1200 rev. 0 | page 6 of 24 absolute maximum ratings table 2. parameter rating supply voltage (v dd ) ?0.3 v to +7.0 v supply voltage (av dd ) ?0.3 v to + 7.0 v input voltage ?0.3 v to v dd + 0.3 v output voltage swing ?0.3 v to v dd + 0.3 v operating temperature range (ambient) ?40c to +125c storage temperature range ?65c to +150c lead temperature soldering vapor phase (60 sec) 215c infrared (15 sec) 220c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad2s1200 rev. 0 | page 7 of 24 pin configuration and function descriptions 04406-0-002 dv dd 1 rd 2 cs 3 sample 4 rdvel 5 soe 6 db11/so 7 db10/sclk 8 db9 9 db8 10 db7 11 reset 33 fs2 32 fs1 31 lot 30 dos 29 dir 28 nm 27 b 26 a 25 cpo 24 dgnd 23 db6 12 db5 13 db4 14 db3 15 dgnd 16 dv dd 17 db2 18 db1 19 db0 20 xtalout 21 clkin 22 refou t 44 refbyp 43 agnd 42 cos 41 coslo 40 av dd 39 sinlo 38 sin 37 agnd 36 exc 35 exc 34 ad2s1200 top view (not to scale) figure 2. pin configuration 44-lead low profile quad flat package [lqfp] (st-44) table 3. pin function descriptions pin no. pin name pin type 1 dv dd supply 2 rd input 3 cs input 4 sample input 5 rdvel input 6 soe input 7 db11/so output 8 db10/sclk input, output 9C15 db9Cdb3 output 16 dgnd ground 17 dv dd supply 18C20 db2Cdb0 output 21 xtalout output 22 clkin input 23 dgnd ground 24 cpo output 25 a output 26 b output pin no. pin name pin type 27 nm output 28 dir output 29 dos output 30 lot output 31 fs1 input 32 fs2 input 33 reset input 34 exc output 35 exc output 36 agnd ground 37 sin input 38 sinlo input 39 av dd supply 40 coslo input 41 cos input 42 agnd ground 43 refbyp input 44 refout output
ad2s1200 rev. 0 | page 8 of 24 resolver format signals 04406-0-003 v r = v p sin( ? t) v b = v s sin( ? t) sin( ) (a) classical resolver s1 s3 v a = v s sin( ? t) cos( ) s2 s4 r1 r2 v r = v p sin( ? t) v b = v s sin( ? t) sin( ) (b) variable reluctance resolver s1 s3 v a = v s sin( ? t) cos( ) s2 s4 r1 r2 figure 3. classical resolver vs. variable reluctance resolver a resolver is a rotating transformer typically with a primary winding on the rotor and two secondary windings on the stator. in the case of a variable reluctance resolver, there are no wind- ings on the rotor as shown in figure 3. the primary winding is on the stator as well as the secondary windings, but the saliency in the rotor design provides the sinusoidal variation in the secondary coupling with the angular position. either way, the resolver output voltages (s3Cs1, s2Cs4) will have the same equations as shown in equation 1. amplitude excitation rotor e frequency excitation rotor t sin angle shaft cos t sin e s s sin t sin e s s = = = = ? = ? 0 0 0 4 2 1 3 equation 1. the stator windings are displaced mechanically by 90 (see figure 3). the primary winding is excited with an ac reference. the amplitude of subsequent coupling onto the stator secon- dary windings is a function of the position of the rotor (shaft) relative to the stator. the resolver, therefore, produces two output voltages (s3Cs1, s2Cs4) modulated by the sine and cosine of shaft angle. resolver format signals refer to the signals derived from the output of a resolver as shown in equation 1. figure 4 illustrates the output format. 04406-0-004 0 s2 to s4 (cos) s3 to s1 (sin) r2 to r4 (ref) 90 180 270 360 figure 4. electrical resolver representation
ad2s1200 rev. 0 | page 9 of 24 principle of operation the ad2s1200 operates on a type ii tracking closed-loop principle. the output continually tracks the position of the resolver without the need for external convert and wait states. as the resolver moves through a position equivalent to the least significant bit weighting, the output is updated by one lsb. the converter tracks the shaft angle by producing an output angle ? that is fed back and compared to the input angle , and the resulting error between the two is driven towards 0 when the converter is correctly tracking the input angle. to measure the error, s3Cs1 is multiplied by cos? and s2Cs4 is multiplied by sin? to give 4 2 3 1 0 0 s to s sin cos t sin e s to s cos sin t sin e the difference is taken, giving ) ( 0 ? sin cos cos sin t sin e equation 2. this signal is demodulated using the internally generated synthetic reference, yielding ) ( 0 sin cos cos sin e ? equation 3. equation 3 is equivalent to e 0 sin ( ? ?), which is approximately equal to e 0 ( ? ?) for small values of ? ?, where ? ? = angular error. the value e 0 ( ? ?) is the difference between the angular error of the rotor and the converters digital angle output. a phase-sensitive demodulator, integrators, and a compensation filter form a closed-loop system that seeks to null the error signal. when this is accomplished, ? equals the resolver angle within the rated accuracy of the converter. a type ii tracking loop is used so that constant velocity inputs can be tracked without inherent error. for more information about the operation of the converter, see the circuit dynamics section. fault detection circuit the ad2s1200 fault detection circuit will detect loss of resolver signals, out of range input signals, input signal mismatch, or loss of position tracking. in these cases, the position indicated by the ad2s1200 may differ significantly from the actual shaft position of the resolver. monitor signal the ad2s1200 generates a monitor signal by comparing the angle in the position register to the incoming sin and cos signals from the resolver. the monitor signal is created in a similar fashion to the error signal described in the principle of operation section. the incoming signals sin and cos are multiplied by the sin and cos of the output angle, respectively, and then added together as shown below: + = cos cos a sin x sin a monitor 2 1 equation 4. where a1 is the amplitude of the incoming sin signal (a1 sin ), a2 is the amplitude of the incoming cos signal (a2 cos ), is the resolver angle, and ? is the angle stored in the position register. note that equation 4 is shown after demodula- tion, with the carrier signal sin t removed. also note that for matched input signal (i.e., no-fault condition), a1 = a2. when a1 = a2 and the converter is tracking ( = ?), the monitor signal output has a constant magnitude of a1 (monitor = a1 (sin 2 + cos 2 ) = a1), independent of shaft angle. when a1 a2, the monitor signal magnitude varies between a1 and a2 at twice the rate of shaft rotation. the monitor signal is used as described in the following sections to detect degradation or loss of input signals. loss of signal detection loss of signal (los) is detected when either resolver input (sin or cos) falls below the specified los sin/cos threshold by comparing the monitor signal to a fixed minimum value. los is indicated by both dos and lot latching as logic low outputs. the dos and lot pins are reset to the no fault state by a rising edge of sample . the los condition has priority over both the dos and lot conditions, as shown in table 4. los is indicated within 45 of angular output error worst case.
ad2s1200 rev. 0 | page 10 of 24 signal degradation detection degradation of signal (dos) is detected when either resolver input (sin or cos) exceeds the specified dos sin/cos threshold by comparing the monitor signal to a fixed maximum value. dos is also detected when the amplitude of the input signals sin and cos mismatch by more than the specified dos sin/ cos mismatch by continuously storing the minimum and maximum magnitude of the monitor signal in internal registers, and calculating the difference between the minimum and maximum. dos is indicated by a logic low on the dos pin, and is not latched when the input signals exceed the maximum input level. when dos is indicated due to mismatched signals, the output is latched low until a rising edge of sample resets the stored minimum and maximum values. the dos condition has priority over the lot condition, as shown in table 4. dos is indicated within 30 of angular output error worst case. loss of position tracking detection loss of tracking (lot) is detected for three separate conditions: ? when the internal error signal of the ad2s1200 has exceeded 5 ? when the input signal exceeds the maximum tracking rate of 60,000 rpm (1,000 rps) ? when the internal position (at the position integrator) differs from the external position (at the position register) by more than 5 lot is indicated by a logic low on the lot pin, and is not latched. lot has a 4 hysteresis, and is not cleared until the internal error signal or internal/external position mismatch is less than 1. when the maximum tracking rate is exceeded, lot is cleared when both the velocity is less than 1,000 rps and the internal/external position mismatch is less than 1. lot can be indicated for step changes in position (such as after a reset signal is applied to the ad2s1200), or for accelerations >~85,000 rps 2 . lot is useful as a built-in test (bit) that the tracking converter is functioning properly. the lot condition has lower priority than both the dos and los conditions as shown in table 4. the lot and dos conditions cannot be indicated at the same time. table 4. fault detection decoding condition dos lot priority loss of signal 0 0 1 degradation of signal 0 1 2 loss of tracking 1 0 3 no fault 1 1 responding to a fault condition if any fault condition (los, dos, or lot) is indicated by the ad2s1200, the output data must be presumed to be invalid. this means that even if a reset or sample pulse releases the fault condition, the output data may be corrupted, even though a fault may not be immediately indicated after the reset / sample event. as discussed earlier, there are some fault conditions with inherent latency. if the device fault is cleared, there could be some latency in the resolvers mechanical position before the fault condition is re-indicated. when a fault is indicated, all output pins will still provide data, although the data may or may not be valid. the fault condition will not force the parallel, serial, or encoder outputs to a known state. however, a new startup sequence is recommended only after a los fault has been indicated. response to specific fault conditions is a system-level requirement. the fault outputs of the ad2s1200 indicate that the device has sensed a potential problem with either the internal or external signals of the ad2s1200. it is the responsibility of the system designer to implement the appropriate fault-handling schemes within the control hardware and/or algorithm of a given application based on the indicated fault(s) and the velocity or position data provided by the ad2s1200. false null condition resolver-to-digital converters that employ type ii tracking loops based on the error equation (equation 3) presented in the principle of operation section can suffer from a condition known as false null. this condition is caused by a metastable solution to the error equation when ? ? = 180. the ad2s1200 is not susceptible to this condition because its hysteresis is implemented externally to the tracking loop. because of the loop architecture chosen for the ad2s1200, the internal error signal always has some movement (1 lsb per clock cycle), and so, in a metastable state, the converter will always move to an unstable condition within one clock cycle, causing the tracking loop to respond to the false null condition as if it were a 180 step change in input position (the response time is the same as specified in dynamic performance section of table 1). therefore, it is impossible to enter the metastable condition any time after the startup sequence as long as the resolver signals are valid. however, in a case of a loss of signal, a full reset is recommended to avoid the possibility of a false null condition. the response to the false null condition has been included in the value of t track provided in the supply sequencing and reset section.
ad2s1200 rev. 0 | page 11 of 24 connecting the converter refer to figure 5. ground should be connected to the agnd pin and dgnd pin. positive power supply v dd = +5 v dc 5% should be connected to the av dd pin and dv dd pin. typical values for the decoupling capacitors are 10 nf and 4.7 f, respectively. these capacitors should be placed as close to the device pins as possible, and should be connected to both av dd and dv dd . if desired, the reference oscillator frequency can be changed from the nominal value of 10 khz using fs1 and fs2. typical values for the oscillator decoupling capacitors are 20 pf. typical values for the reference decoupling capacitors are 10 f and 0.01 f, respectively. 04406-0-005 dv dd 5v 1 2 3 4 5 6 7 8 9 10 11 reset 33 32 31 30 29 28 27 26 25 24 dgnd 8.912 mhz 20pf 20pf 4.7 f 10nf 23 12 13 14 15 dgnd 16 dv dd 17 18 19 20 21 22 44 refbyp 43 agnd 42 cos 41 coslo 40 av dd 39 sinlo 38 sin 37 agnd 36 35 exc 34 ad2s1200 exc 10 f 10nf 5v s2 s6 s3 s1 4.7 f 10nf 5v buffer circuit buffer circuit r2 r1 figure 5. connecting the ad2s1200 to a resolver the gain of the buffer depends on the type of resolver used. since the specified excitation output amplitudes are matched to the specified sin/cos input amplitudes, the gain of the buffer is determined by the attenuation of the resolver. in this recommended configuration, the converter introduces a v ref /2 offset in the sin, cos signals coming from the resolver. of course, the sinlo and coslo signals may be connected to a different potential relative to ground, as long as the sin and cos signals respect the recommended specifications. note that since the exc/ exc outputs are differential, there is an inherent gain of 2. for example, if the primary to secondary turns ratio is 2:1, the buffer will have unity gain. likewise, if the turns ratio is 5:1, the gain of the buffer should be 2.5. figure 6 suggests a buffer circuit. the gain of the circuit is ) 1 / 2 ( r r gain ? = and ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = in ref out v r r r r v v 1 2 1 2 1 v ref is set so that v out is always a positive value, eliminating the need for a negative supply. 04406-0-006 12v exc/exc (v in ) 5v (v ref ) r2 12v v out 33 ? 33 ? r1 442 ? 1.24k ? 12v 2.7k ? 2.7k ? figure 6. buffer circuit separate screened twisted cable pairs are recommended for analog inputs sin/sinlo and cos/coslo. the screens should terminate to refout. to achieve the dynamic performance specified, an 8.192 mhz crystal must be used.
ad2s1200 rev. 0 | page 12 of 24 absolute position and velocity output the angular position and angular velocity are represented by binary data and can be extracted either via a 12-bit parallel interface or a 3-wire serial interface that operates at clock rates up to 25 mhz. the chip select pin, cs , must be held low to enable the device. angular position and velocity can be selected using a dedicated polarity input, rdvel . soe input the serial output enable pin, soe , is held high to enable the parallel interface. the soe pin is held low to enable the serial interface, which places pins (db0Cdb9) in the high impedance state, while db11 is the serial output (so), and db10 is the serial clock input (sclk). data format the digital angle signal represents the absolute position of the resolver shaft as a 12-bit unsigned binary word. the digital velocity signal is a 12-bit twos complement word, which represents the velocity of the resolver shaft rotating in either a clockwise or a counterclockwise direction. finally, the rd input is used to read the data from the output register and to enable the output buffer. the timing requirements for the read cycle are illustrated in figure 7. sample input data is transferred from the position and velocity integrators respectively to the position and velocity registers following a high to low transition of the sample signal. this pin must be held low for at least t 1 ns to guarantee correct latching of the data. rd should not be pulled low before this time. also, a rising edge of sample resets the internal registers that contain the minimum and maximum magnitude of the monitor signal. parallel interface the angular position and angular velocity are available on the ad2s1200 in two 12-bit registers, which can be accessed via the 12-bit parallel port. the parallel interface is selected holding the soe pin high. data is transferred from the velocity and position integrators, respectively, to the position and velocity registers following a high-to-low transition on the sample pin. the rdvel polarity pin selects which register from the position or the velocity registers is transferred to the output register. the cs pin must be held low to transfer the selected data register to the output register. finally, the rd input is used to read the data from the output register and to enable the output buffer. the timing requirements for the read cycle are shown in figure 7. sample input data is transferred from the position and velocity integrators, respectively, to the position and velocity registers following a high-to-low transition on the sample signal. this pin must be held low for at least t 1 ns to guarantee correct latching of the data. rd should not be pulled low before this time since data would not be ready. the converter will continue to operate during the read process. also, a rising edge of sample resets the internal registers that contain the minimum and maximum magnitude of the monitor signal. cs input the device will be enabled when cs is held low. rdvel input rdvel input is used to select between the angular position and velocity registers as shown in figure 7. rdvel is held high for angular position and low for angular velocity. the rdvel pin must be set (stable) at least t 4 ns before the rd pin is pulled low. rd input the 12-bit data bus lines are normally in a high impedance state. the output buffer is enabled when cs and rd are held low. a falling edge of the rd signal transfers data to the output buffer. the selected data is made available to the bus to be read within t 6 ns of the rd pin going low. the data pins will return to high impedance state when the rd returns to high state, within t 7 ns. if the user is reading data continuously, rd can be reapplied a minimum of t 5 ns after it was released.
ad2s1200 rev. 0 | page 13 of 24 04406-0-007 t 3 t 6 t 7 t ck clkin data don't care vel pos t 2 sample cs rd rdvel t 1 t 1 t 3 t 5 t 4 t 5 t 4 t 7 t 6 figure 7. parallel port read timing table 5. parallel port timing parameter description min typ max t ck clock period (= 1/8.192 mhz) ~122 ns t 1 sample pulse width 2 t ck + 20 ns t 2 delay from sample before rd /cs low 6 t ck + 20 ns t 3 rd pulse width 18 ns t 4 set time rdvel before rd /cs low 5 ns t 5 hold time rdvel after rd /cs low 7 ns t 6 enable delay rd /cs low to data valid 12 ns t 7 disable delay rd /cs low to data high z 18 ns
ad2s1200 rev. 0 | page 14 of 24 serial interface the angular position and angular velocity are available on the ad2s1200 in two 12-bit registers. these registers can be accessed via a 3-wire serial interface, so, rd , and sclk, that operates at clock rates up to 25 mhz and is compatible with spi and dsp interface standards. the serial interface is selected by holding low the soe pin. data from the position and velocity integrators are first transferred to the position and velocity registers, using the sample pin. the rdvel polarity pin selects which register from the position or the velocity registers is transferred to the output register. the cs pin must be held low to transfer the selected data register to the output register. finally, the rd input is used to read the data that will be clocked out of the output register and will be available on the serial output pin, so. when the serial interface is selected, db11 is used as the serial output pin, so, and db10 is used as the serial clock input, sclk, while pins db0Cdb9 are placed in the high impedance state. the timing requirements for the read cycle are described in figure 8. so output the output shift register is 16-bit wide. data is shifted out of the device as a 16-bit word under the control of the serial clock input, sclk. the timing diagram for this operation is shown in figure 8. the 16-bit word consists of 12 bits of angular data (position or velocity depending on rdvel input), one rdvel status bit and three status bits, a parity bit, degradation of signal bit, and loss of tracking bit. data is read out msb first (bit 15) on the so pin. bit 15 through bit 4 correspond to the angular information. the angular position data format is unsigned binary, with all zeros corresponding to 0 degrees and all ones corresponding to 360 degrees Cl lsb. the angular velocity data format instead is twos complement binary, with the msb representing the rotation direction. bit 3 is the rdvel status bit, 1 indicating position and 0 indicating velocity. bit 2 is dos, the degradation of signal flag (refer to the fault detection circuit section). bit 1 is lot, the loss of tracking flag (refer to the fault detection circuit section). bit 0 is par, the parity bit: both position and velocity data are odd parity format; the data read out will always contain an odd number of logic highs (1s). sample input data is transferred from the position and velocity integrators, respectively, to the position and velocity registers following a high-to-low transition on the sample signal. this pin must be held low for at least t 1 ns to guarantee correct latching of the data. rd should not be pulled low before this time since data would not be ready. the converter will continue to operate during the read process. cs input the device will be enabled when cs is held low. rd input the 12-bit data bus lines are normally in a high impedance state. the output buffer is enabled when cs and rd are held low. the rd input is an edge-triggered input that acts as frame synchronization signal and output enable. a falling edge of the rd signal transfers data to the output buffer and data will be available on the serial output pin, so. rd must be held low for t 9 before the data is valid on the outputs. after rd goes low, the serial data will be clocked out of the so pin on the falling edges of the sclk (after a minimum of t 10 ns): the msb will be already available at the so pin on the very first falling edge of the sclk. each other bit of the data word will be shifted out on the rising edge of sclk and will be available at the so pin on the falling edge of sclk for the next 15 clock pulses. the high-to-low transition of rd must happen during the high time of the sclk to avoid msb being shifted on the first rising edge of the sclk and lost. rd may rise high after the falling edge of the last bit transmitted. subsequent negative edges greater than the defined word length will clock zeros from the data output if rd remains in a low state. if the user is reading data continuously, rd can be reapplied a minimum of t 5 ns after it is released. rdvel input rdvel input is used to select between the angular position and velocity registers. rdvel is held high for angular position and low for angular velocity. the rdvel pin must be set (stable) at least t 4 ns before the rd pin is pulled low.
ad2s1200 rev. 0 | page 15 of 24 t 11 t sclk t 10 t 9 t 8 04406-0-008 sclk so msb msb?1 lsb rdvel dos lot par rd t 3 t 6 t 7 t ck clkin so vel pos t 2 sample cs rd rdvel t 1 t 1 t 3 t 5 t 4 t 5 t 4 t 7 t 6 figure 8. serial port read timing table 6. serial port timing parameter description min typ max t 8 msb read time from rd /cs to sclk 15 ns t sclk t 9 enable time rd /cs to db valid 12 ns t 10 delay sclk to db valid 14 ns t 11 disable time rd /cs to db high z 18 ns t sclk serial clock period (25 mhz max) 40 ns
ad2s1200 rev. 0 | page 16 of 24 incremental encoder outputs the incremental encoder emulation outputs a, b, and nm are free running and are always valid, providing that valid resolver format input signals are applied to the converter. the ad2s1200 emulates a 1024-line encoder. relating this to converter resolution means one revolution produces 1,024 a, b pulses. a leads b for increasing angular rotation (i.e., clockwise direction). the addition of the dir output negates the need for external a and b direction decode logic. the dir output indicates the direction of the input rotation and it is high for increasing angular rotation. dir can be considered as an asynchronous output and can make multiple changes in state between two consecutive lsb update cycles. this occurs when the direction of rotation of the input changes but the magnitude of the rotation is less than 1 lsb. the north marker pulse is generated as the absolute angular position passes through zero. the north marker pulse width is set internally for 90 and is defined relative to the a cycle. figure 9 details the relationship between a, b, and nm. 04406-0-009 a b nm figure 9. a, b, and nm timing for clockwise rotation unlike incremental encoders, the ad2s1200 encoder output is not subject to error specifications such as cycle error, eccentric- ity, pulse and state width errors, count density, and phase ?. the maximum speed rating, n , of an encoder is calculated from its maximum switching frequency, f max , and its pulses per revo- lution ( ppr ). ppr f n max = 60 the ad2s1200 a, b pulses are initiated from xtalout, which has a frequency of 4.096 mhz. the equivalent encoder switching frequency is ) 1 4 ( 024 . 1 096 . 4 4 / 1 pulse updates mhz mhz = = at 12 bits, the ppr = 1,024. therefore, the maximum speed, n , of the ad2s1200 is rpm n 60000 024 , 1 000 , 024 , 1 60 = = to get a maximum speed of 60,000 rpm, an external crystal of 8.192 mhz has to be chosen in order to produce an internal clockout equal to 4.096 mhz. this compares favorably with encoder specifications where f max is specified from 20 khz (photo diodes) to 125 khz (laser based) depending on the light system used. a 1,024 line laser- based encoder will have a maximum speed of 7,300 rpm. the inclusion of a, b outputs allows the ad2s1200 plus resolver solution to replace optical encoders directly without the need to change or upgrade existing application software. on-board programmable sinusoidal oscillator an on-board oscillator provides the sinusoidal excitation signal (exc) to the resolver as well as its complemented signal ( exc ). the frequency of this reference signal is programmable to four standard frequencies (10 khz, 12 khz, 15 khz, or 20 khz) using the fs1 and fs2 pins (see table 7). fs1 and fs2 have internal pull- ups, so the default frequency is 10 khz. the amplitude of this signal is centered on 2.5 v and has an amplitude of 3.6 v p-p. table 7. excitation frequency selection frequency selection (khz) fs1 fs2 10 1 1 12 1 0 15 0 1 20 0 0 the reference output of the ad2s1200 will need an external buffer amplifier to provide gain and the additional current to drive a resolver. refer to figure 6 for a suggested buffer circuit. the ad2s1200 also provides an internal synchronous reference signal that is phase locked to its sin and cos inputs. phase errors between the resolver primary and secondary windings could degrade the accuracy of the rdc and are compensated by this synchronous reference signal. this also compensates the phase shifts due to temperature and cabling and eliminates the need of an external preset phase compensation circuits.
ad2s1200 rev. 0 | page 17 of 24 synthetic reference generation when a resolver undergoes a high rotation rate, the rdc tends to act as an electric motor and produces speed voltages, along with the ideal sin and cos outputs. these speed voltages are in quadrature to the main signal waveform. moreover, nonzero resistance in the resolver windings causes a non-zero phase shift between the reference input and the sin and cos outputs. the combination of speed voltages and phase shift causes a tracking error in the rdc that is approximated by frequency reference rate rotation shift phase error = to compensate for the described phase error between the resolver reference excitation and the sin/cos signals, an internal synthetic reference signal is generated in phase with the refer- ence frequency carrier. the synthetic reference is derived using the internally filtered sin and cos signals. it is generated by determining the zero crossing of either the sin or cos (which- ever signal is larger, to improve phase accuracy) and evaluating the phase of the resolver reference excitation. the synthetic reference reduces the phase shift between the reference and sin/cos inputs to less than 10, and will operate for phase shifts of 45. supply sequencing and reset the ad2s1200 requires an external reset signal to hold the reset input low until v dd is within the specified operating range of 4.5 v to 5.5 v. the reset pin must be held low for a minimum of 10 s after v dd is within the specified range (t rst in figure 10). applying a reset signal to the ad2s1200 initializes the output position to a value of 0x000 (degrees output through the parallel, serial, and encoder interfaces) and causes los to be indicated (lot and dos pins pulled low) as shown in figure 10. failure to apply the above (correct) power-up/reset sequence can result in an incorrect position indication. after a rising edge on the reset input, the device must be allowed at least 20 ms (t track ) as shown in figure 10 for internal circuitry to stabilize and the tracking loop to settle to the step change in input position. after t track , a sample pulse must be applied, releasing the lot and dot pins to the state deter- mined by the fault detection circuitry and providing valid position data at the parallel and serial outputs (note that if position data is being acquired via the encoder outputs, they may be monitored during t track ). the reset pin is internally pulled up. t rst t rst 04406-0-010 v dd reset 4.75v valid output data sample lot dos t track figure 10. power supply sequencing and reset charge pump output a 204.8 khz square wave output with 50% duty cycle is avail- able at the cpo output pin of the ad2s1200. this square wave output can be used for negative rail voltage generation, or to create a v cc rail.
ad2s1200 rev. 0 | page 18 of 24 circuit dynamics ad2s1200 loop response model 04406-0-011 error (acceleration) ? out velocity k1 k2 1?z ?1 1?bz ?1 1?z ?1 c1?az ?1 c sin/cos lookup figure 11. rdc system response block diagram the rdc is a mixed-signal device, which uses two a/d converters to digitize signals from the resolver and a type ii tracking loop to convert these to digital position and velocity words. the first gain stage consists of the adc gain on the sin/cos inputs, and the gain of the error signal into the first integrator. the first integrator generates a signal proportional to velocity. the compensation filter contains a pole and a zero, used to provide phase margin and reduce high frequency noise gain. the second integrator is the same as the first integrator and generates the output position from the velocity signal. the sin/cos lookup has unity gain. values are given below for each section: ? adc gain parameter (k1 nom = 1.8/2.5) ) ( ) ( 1 v v v v k ref p in = ? error gain parameter = 2 10 18 2 6 x k ? compensator zero coefficient 4096 4095 = a ? compensator pole coefficient 4096 4085 = b ? integrator gain parameter 4096000 1 = c ? int1 and int2 transfer function 1 1 ) ( ? ? = z c z i ? compensation filter transfer function 1 1 1 1 ) ( ? ? ? ? = bz az z c ? r2d open-loop transfer function ) ( ) ( 2 1 ) ( 2 z c z i k k z g = ? r2d closed-loop transfer function ) ( 1 ) ( ) ( z g z g z h + = the closed-loop magnitude and phase responses are that of a second-order low-pass filter (see figure 12 and figure 13). to convert g(z) into the s-plane, we perform an inverse bilinear transformation by substituting for z, where t = the sampling period (1/4.096 mhz 244 ns). s t s t z ? + = 2 2 substitution yields the open-loop transfer function g(s). ) 1 ( 2 ) 1 ( 1 ) 1 ( 2 ) 1 ( 1 4 1 ) 1 ( 2 1 ) ( 2 2 2 b b t s a a t s s t s st b a a k k s g ? + + ? + + + + ? ? = this transformation produces the best matching at low frequencies (f << f sample ). at lower frequencies (within the closed-loop bandwidth of the ad2s1200), the transfer function can be simplified to 2 1 2 1 1 ) ( st st s k s g a + + ? where: b a a k k k b b t t a a t t a ? ? = ? + = ? + = ) 1 ( 2 1 ) 1 ( 2 ) 1 ( ) 1 ( 2 ) 1 ( 2 1 solving for each value gives t 1 = 1 s, t 2 = 90 s, and k a 7.4 10 6 s - 2 . note that the closed-loop response is described as ) ( 1 ) ( ) ( s g s g s h + = by converting to the s-domain, we are able to quantify the open-loop dc gain (k a ). this value is useful during calculation of acceleration error of the loop as discussed in the sources of error section. the step response to a 10 input step is shown in figure 14. because the error calculation (equation 3) is nonlinear for large values of ? ?, the response time for larger step changes in position (90 ? 180) will typically take three times as long as the response to a small step change in position (<20). in response to a step change in velocity, the ad2s1200 will exhibit the same response characteristics as for a step change in position.
ad2s1200 rev. 0 | page 19 of 24 04406-0-012 1 5 ?0 ?40 ?35 ?30 ?25 ?20 magnitude (db) ?15 ?10 ?5 ?45 10 100 10k 1k frequency (hz) 100k figure 12. rdc system magnitude response 04406-0-013 1 0 ?20 ?180 ?160 ?140 ?120 ?100 phase (degrees) ?80 ?60 ?40 ?200 10 100 10k 1k frequency (hz) 100k figure 13. rdc system phase response 04406-0-014 0 20 18 2 4 6 8 10 angle (degrees) 12 14 16 0 12 4 3 time (ms) 5 figure 14. rdc small step response sources of error acceleration a tracking converter employing a type ii servo loop does not suffer any velocity lag. there is, however, an error associated with acceleration. this error can be quantified using the acceleration constant (k a ) of the converter. error tracking on accelerati input k a = conversely, a k on accelerati input error tracking = figure 15 shows tracking error versus acceleration for the ad2s1200. the numerator and denominators units must be consistent. the maximum acceleration of the ad2s1200 has been defined as the acceleration that creates an output position error of 5 (when lot is indicated). the maximum acceleration can be calculated as 2 2 000 , 103 ) / ( 360 5 ) (sec rps rev k on accelerati maximum a ? = ? the ad2s1200 will be able to withstand the maximum acceleration of 103,000 rps 2 for approximately 10 ms before reaching its maximum tracking rate of 1,000 rps. ms rps rps 10 ) ( 000 , 103 ) ( 000 , 1 2 ? 04406-0-015 0 10 9 1 2 3 4 5 tracking error (degrees) 6 7 8 0 40k 80k 160k 120k acceleration (rps 2 ) 200k figure 15. tracking error vs. acceleration
ad2s1200 rev. 0 | page 20 of 24 clock requirements to achieve the specified dynamic performance, an external crystal of 8.192 mhz must be used at the clkin, xtalout pins. the position and velocity accuracy are guaranteed for operation with a 8.192 mhz clock. however, the position accuracy will still be maintained for clock frequencies 10% around this value. the velocity outputs are scaled in proportion to the clock frequency so that if the clock is 10% higher than the nominal, the full-scale velocity will be 10% higher than nominal. the maximum tracking rate and the tracking loop bandwidth also vary with the clock frequency. connecting to the dsp the ad2s1200 serial port is ideally suited for interfacing to dsp configured microprocessors. figure 16 shows the ad2s1200 interfaced to admc401, one of the dsp based motor controllers. the on-chip serial port of the admc401 is used in the following configuration: ? alternate framing transmit mode with internal framing (internally inverted) ? normal framing receive mode with external framing (internally inverted) ? internal serial clock generation in this mode, the admc401 uses the internal tfs signal as external rfs to fully control the timing of receiving data and it uses the same tfs as rd to the ad2s1200. the admc401 also provides an internal continuous serial clock to the ad2s1200. the sample signal on the ad2s1200 could be provided either by using a pio or by inverting the pwmsync signal to synchronize the position and velocity reading with the pwm switching frequency. cs and rdvel may be obtained using two pio outputs of the admc401. the 12 bits of significant data plus status bits are available on each consecutive negative edge of the clock following the low going of the rd signal. data is clocked from the ad2s1200 into the data receive register of the admc401. this is internally set to 16 bits (12 bits data, 4 status bits) because 16 bits are received overall. the serial port automatically generates an internal processor interrupt. this allows the admc401 to read 16 bits at once and continue processing. all admc401 products can interface to the ad2s1200 with similar interface circuitry. 04406-0-016 sclk dr tfs rfs pwmsync pio pio sclk soe so rd sample cs rdvel admc401 ad2s1200 figure 16. connecting to the admc401
ad2s1200 rev. 0 | page 21 of 24 outline dimensions view a top view (pins down) 11 1 44 34 33 23 22 12 0.80 bsc 12.00 bsc 10.00 bsc 1.60 max seating plane 0.75 0.60 0.45 0.45 0.37 0.30 pin 1 0.20 0.09 1.45 1.40 1.35 0.10 max coplanarity view a rotated 90 ccw seating plane 10 6 2 7 3.5 0 0.15 0.05 compliant to jedec standards ms-026bcb figure 17. 44-lead low profile quad flat package [lqfp] (st-44) dimensions shown in millimeters ordering guide model temperature range angular accuracy package description package option ad2s1200yst ?40c to +125c 11 arc min 44-lead lo w profile quad flat package (lqfp) st-44 ad2s1200wst ?40c to +125c 22 arc min 44-lead lo w profile quad flat package (lqfp) st-44
ad2s1200 rev. 0 | page 22 of 24 notes
ad2s1200 rev. 0 | page 23 of 24 notes
ad2s1200 rev. 0 | page 24 of 24 notes ? 2003 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. c04406-0-10/03(0)

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